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| PKS603-607 PeakSwitchTM Family Product Highlights EcoSmart - Extremely Energy-Efficient * Standbyoutputpower0.6Wfor1Winput(highline) * Sleepmodepower2.4Wat3Winput(highline) * No-loadconsumption<200mWat265VACinput * SurpassesCaliforniaEnergyCommission(CEC), ENERGYSTAR,andEUrequirements PeakSwitch Features Reduce System Cost * Deliverspeakpowerofuptothreetimesmaximum continuousoutputpower * 277kHzoperationduringpeakpowersignificantly reducestransformersize * ProgrammablesmartAClinesensingprovideslatching shutdownduringshortcircuit,overloadandopenloop faults,andpreventsglitchesduringpowerdownor brownout * TwoexternalcomponentsresetlatchonACremoval * Adaptiveswitchingcycleon-timeextensionincreaseslow linepeakoutputpower,minimizingbulkcapacitorsize * Adaptivecurrentlimitreducesoutputoverloadpower * FrequencyjitteringreducesEMIfiltercost * TightI2ftolerancesandnegligibletemperaturevariation ofkeyparameterseasedesignandlowercost * Accuratehystereticthermalshutdownwithautomatic recoveryprovidescompletesystemleveloverload protectionandeliminatesneedformanualreset Better System Cost/Performance over RCC & Discrete * SimpleON/OFFcontrol-noloopcompensationneeded * Verylowcomponentcount-higherreliabilityandsingle sideprintedcircuitboard * Highbandwidthprovidesfastturnonwithnoovershoot andexcellenttransientloadresponse * Peakcurrentlimitoperationrejectslinefrequencyripple * Built-incurrentlimitandhystereticthermalprotection Applications * Inkjetprinter * Datastorage,audioamplifier,DCmotordrives (R) Enhanced, Energy-Efficient, Off-Line Switcher IC With Super Peak Power Performance AC IN + DC OUT Optional Smart AC Sense PeakSwitch D EN/UV BP S PI-3995-051006 Figure 1. Typical Peak Power Application. PRODUCT3 PKS603 P PKS604 P PKS604 Y/F PKS605 P PKS605 Y/F PKS606 P PKS606 Y/F PKS607 Y/F Table 1. OUTPUT POWER TABLE 85-265 VAC 230 VAC 15% Adapter Adapter Adapter Adapter Cont.1 Peak2 Cont.1 Peak2 13 W 23 W 35 W 31 W 46 W 35 W 68 W 75 W 32 W 56 W 56 W 60 W 79 W 66 W 117 W 126 W 9W 16 W 23 W 21 W 30 W 25 W 45 W 50 W 25 W 44 W 44 W 44 W 58 W 46 W 86 W 93 W Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at +50 C ambient. 2. Typical peak power for a period of 100 ms and a duty cycle of 10% in a non-ventilated enclosed adapter measured at +50 C (see Key Applications section for details). 3. See Part Ordering Information. Description PeakSwitchisdesignedtoaddressapplicationswithhighpeakto-continuouspowerratiodemands.Theveryhighswitching frequencyduringpeakpowerloadsandexcellentloadtransient responsereducesystemcostaswellascomponentcountandsize. PeakSwitchincorporatesa700VpowerMOSFET,oscillator, highvoltageswitchedcurrentsourceforstartup,currentlimit, andthermalshutdownontoamonolithicdevice.Inaddition, thesedevicesincorporateauto-restart,lineunder-voltagesense andfrequencyjittering.Aninnovativedesignminimizesaudio frequencycomponentsinthesimpleON/OFFcontrolscheme topracticallyeliminateaudiblenoisewithstandardvarnished transformerconstruction. October 2006 PKS603-607 BYPASS (BP) REGULATOR 5.8 V LINE UNDER-VOLTAGE DRAIN (D) 240 A 25 A LATCH OFF/ AUTORESTART COUNTER ON TIME EXT RESET FAULT PRESENT + BYPASS PIN UNDER-VOLTAGE 6.3 V CURRENT LIMIT STATE MACHINE/ ADAPTIVE CURRENT LIMIT - 5.8 V 4.8 V VI LIMIT CURRENT LIMIT COMPARATOR + ENABLE JITTER CLOCK 1.0 V + VT DCMAX OSCILLATOR ENABLE/ UNDERVOLTAGE (EN/UV) 1.0 V S Q THERMAL SHUTDOWN R Q LEADING EDGE BLANKING SOURCE (S) GROUND (GND) (Y & F Package Only) PI-3940-040606 Figure 2. Functional Block Diagram. Pin Functional Description Y Package (TO-220-7C) Tab Internally Connected to SOURCE Pin 7D 5 NC 4S 3 EN/UV 2 GND 1 BP DRAIN (D) Pin: The power MOSFET drain connection provides internal operatingcurrentforbothstartupandsteady-stateoperation. BYPASS (BP) Pin: A0.33Fexternalbypasscapacitorfortheinternallygenerated 5.8Vsupplyisconnectedtothispin.Intypicalapplications, thispinmustbeexternallysuppliedviaabiaswinding. ENABLE/UNDER-VOLTAGE (EN/UV) Pin: Thispinhasdualfunctions:enableinputandlineunder-voltage sense.Duringnormaloperation,switchingofthepowerMOSFET iscontrolledbythispin.MOSFETswitchingisdisabledwhena currentgreaterthan240Aisdrawnfromthispin.Thispinmay also sense line under-voltage conditions through either an external resistor connected to the DC line voltage or anAC sensecircuit. SOURCE (S) Pin: ThisistheMOSFETsourceconnectionforhighvoltagereturn andcontrolcircuitcommon. P Package (DIP-8C) BP EN/UV 1 2 8 7 6 D 4 5 S S S S F Package (TO-262-7C) 7D 5 NC 4S 3 EN/UV 2 GND 1 BP PI-3941-031506 Figure 3. Pin Configuration. GROUND (GND) Pin (Y or F Package Only): This is the signal ground for the bypass capacitor and optocoupler. 2 Rev. I 10/06 PKS603-607 PeakSwitch Functional Description PeakSwitchintegratesa700VpowerMOSFETswitchwitha powersupplycontrolleronthesamedie.Unlikeconventional pulsewidthmodulation(PWM)controllers,PeakSwitchusesa simpleON/OFFcontroltoregulatetheoutputvoltage. The controller consists of an oscillator, enable circuit (sense and logic), current-limit state machine, 5.8 V regulator, BYPASS pin under-voltage circuit, over- temperature protection, current limit circuit, and leading edge blanking. PeakSwitch incorporates additional circuitry for adaptive current limit, line under-voltage sense, programmable smart line sense, auto-restart, adaptive switching cycle on-time extension, and frequency jitter. Figure 2 is a functional block diagram of the device's most importantfeatures. Oscillator Thetypicaloscillatorfrequencyisinternallysettoanaverage of277kHz.Twosignalsaregeneratedfromtheoscillator:the maximumdutycycle(DCMAX)signalandtheclocksignalthat indicatesthebeginningofeachcycle. The oscillator incorporates circuitry that introduces a small amountoffrequencyjitter,typically16kHzpeak-to-peak,to minimizeEMIemission.Themodulationrateofthefrequency jitter is set to 1.1 kHz to optimize EMI reduction for both averageandquasi-peakemissions.Thefrequencyjittershould bemeasuredwiththeoscilloscopetriggeredatthefallingedge oftheDRAINwaveform.ThewaveforminFigure4illustrates thefrequencyjitter. Enable Input and Current-Limit State Machine TheenableinputcircuitattheEN/UVpinconsistsofalow impedance source follower output set at 1.0 V. The current PI-3942-022806 throughthesourcefollowerislimitedto240A.Whenthe current out of this pin exceeds 240A, a low logic level (disable)isgeneratedattheoutputoftheenablecircuit.This enable circuit output is sampled at the beginning of each cycleontherisingedgeoftheclocksignal.Ifhigh,thepower MOSFETisturnedonforthatcycle(enabled).Iflow,thepower MOSFETremainsoff(disabled).Sincethesamplingisdone onlyatthebeginningofeachcycle,subsequentchangesinthe EN/UV pin voltage or current during the remainder of the cycleareignored. The current-limit state machine reduces the current limit by discrete amounts at light loads when PeakSwitch is likely to switchintheaudiblefrequencyrange.Thelowercurrentlimit raisestheeffectiveswitchingfrequencyabovetheaudiorange andreducesthetransformerfluxdensity,includingtheassociated audible noise. The state machine monitors the sequence of EN/UVpinvoltagelevelstodeterminetheloadconditionand adjuststhecurrentlimitlevelaccordinglyindiscreteamounts. Undermostoperatingconditions(exceptwhenclosetono-load), thelowimpedanceofthesourcefollowerkeepsthevoltageon theEN/UVpinfromgoingmuchbelow1.0Vinthedisabled state.Thisimprovestheresponsetimeoftheoptocouplerthat isusuallyconnectedtothispin. 5.8 V Regulator and 6.3 V Shunt Voltage Clamp The5.8Vregulatorchargesthebypasscapacitorconnectedto theBYPASSpinto5.8Vbydrawingacurrentfromthevoltage ontheDRAINpinwhenevertheMOSFETisoff.TheBYPASS pinistheinternalsupplyvoltagenode.WhentheMOSFET ison,thePeakSwitch operatesfromtheenergystoredinthe bypasscapacitor.ThevoltageontheDRAINpinpowersthe bypassduringstart-up. Thereisa6.3VshuntregulatorclampingtheBYPASSpinat 6.3V when current is provided through an external resistor from the bias winding in normal operation. Powering the PeakSwitchdeviceinthiswayminimizesno-loadconsumption toabout150mWat265VAC.Notethatabiaswindingmustbe usedtopowerthedevice.SeeKeyApplicationConsiderations sectionfordetails. BYPASS Pin Under-Voltage TheBYPASSpinunder-voltagecircuitrydisablesthepower MOSFETwhentheBYPASSpinvoltagedropsbelow4.8V. OncetheBYPASSpinvoltagedropsbelow4.8V,itmustrise backto5.8Vtoenable(turnon)thepowerMOSFET. 600 500 VDRAIN 400 300 200 100 0 285 kHz 269 kHz 0 2.5 Time (s) 5 Figure 4. Frequency Jitter. Over Temperature Protection The thermal shutdown circuitry senses the die temperature. Thethresholdistypicallysetat142Cwith75Chysteresis. When the die temperature rises above this threshold, the powerMOSFETisdisabledandremainsdisableduntilthedie temperaturefallsby75C,atwhichpointitisre-enabled.Alarge 3 Rev. I 10/06 PKS603-607 hysteresisof75C(typical)isprovidedtopreventoverheating ofthePCboardduringacontinuousfaultcondition. Current Limit ThecurrentlimitcircuitsensesthecurrentinthepowerMOSFET. Whenthiscurrentexceedstheinternalthreshold(ILIMIT),the powerMOSFETisturnedofffortheremainderofthatcycle.The currentlimitstatemachinereducesthecurrentlimitthreshold bydiscreteamountsundermediumandlightloads. The leading edge blanking circuit inhibits the current limit comparatorforashorttime(tLEB)afterthepowerMOSFETis turnedon.Thisleadingedgeblankingtimehasbeensetsothat currentspikescausedbycapacitanceandsecondary-siderectifier reverserecoverytimewillnotcauseprematureterminationof theMOSFETconductionportionoftheswitchingcycle. During startup and fault conditions, the controller prevents excessive drain currents by reducing the switching frequency. Adaptive Current Limit Whenswitchinginthefullcurrentlimitstate,askippedcycle followed by a cycle that terminates at the full current limit impliesthatthelinevoltageisathighline.Underthiscondition, adaptive current limit reduces the full current limit level by approximately10%inordertoreduceoutputoverloadpower. The next skipped cycle disables the adaptive current limit conditionandrestoresthefullcurrentlimitlevel. Line Under-Voltage Sense Circuit The line under-voltage circuit prevents startup below the programmedinputvoltagebyconnectinganexternalresistor from either the DC line or from an AC sense circuit (see Figure1)totheEN/UVpin.Thecompletefunctionisdescribed intheflowchartshowninFigure5.Duringpoweruporwhen theswitchingofthepowerMOSFETisdisabledinauto-restart, thecurrentflowingintotheEN/UVpinmustexceed25Ato initiateswitchingofthepowerMOSFET.Duringpowerup, oncethethresholdisexceeded,theBypasspinmustchargefrom 4.8Vto5.8VbeforeMOSFETswitchingisinitiated. The line under-voltage circuit also detects when there is no externalresistorconnectedtotheEN/UVpin(lessthan~1A intopin).Inthiscase,thelineunder-voltagefunctionisdisabled andthedeviceoperateswithanormalauto-restartfunction. Programmable Smart AC Line Sense WhenanexternalACsensecircuitisused(seeFigure1),theline under-voltagesensecircuitcanbeusedtodeterminethereason foralossoffeedbacksignalattheEN/UVpin.Intheeventof afaultconditionsuchasoutputoverload,outputshortcircuit, oranopenloopcondition,thepowerMOSFETswitchingis disabledaftertheEN/UVpinisnotpulledlowfor30ms.Ifthe AClineispresent(IEN>25A)atthetimeswitchingisdisabled, 1. Startup 2. UV Resistor Present? No 9. Start Switching Yes No No 3. AC Input Present? (IEN>25 A) 10. No Feedback >30 ms? Yes Yes 11. Stop Switching (for 5 s) 4. Start Switching No 5. No Feedback >30 ms? Yes 6. Stop Switching Yes 7. AC Input Present? (IEN>25 A) Note: Normal operation (no fault present) is denoted by looping with a "No" response at decision box 5 or 10. No 8. Reset A/R Latch PI-4014-062305 Figure 5. PeakSwitch Line Sense Function Flow Chart. Rev. I 10/06 PKS603-607 VDRAIN PI-3943-031506 300 200 100 0 10 peakoutputpowerwasrequiredinlowlineconditions.On-time extensionisdisabledduringthestartupofthepowersupply. PeakSwitch Operation PeakSwitchdevicesoperateinthecurrent-limitmode.When enabled, the oscillator turns the power MOSFET on at the beginningofeachcycle.TheMOSFETisturnedoffwhenthe currentrampsuptothecurrentlimitorwhentheDCMAXlimit isreached.Sincethehighestcurrentlimitlevelandfrequency VDC-OUTPUT 5 0 V EN CLOCK D 0 5 10 Time (s) Figure 6. PeakSwitch Auto-Restart Operation. the line under-voltage sense circuit prevents a restart attempt until the AC input voltage is removed (IEN <25A).Thentheinternalauto-restartlatchisresetand thepowerMOSFETswitchingwillresumeoncetheACinput voltageisappliedagain(IEN>25A).Thiseffectivelyprovides alatchingshutdownfunctionwithACresetduringsuchafault condition. Whenabrownoutorlinesagoccurs,outputregulationmaybe lostandtheEN/UVpinwillreceivenofeedback(itispulled low).After30msofnofeedback,MOSFETswitchingisdisabled. SincetheAClineisabnormallylow(IEN<25A)MOSFET switchingremainsdisableduntilnormallinevoltageisrestored. ThepowerMOSFETswitchingwillresumeoncetheACinput returnstonormal(IEN>25A).Thiseffectivelydisablesthe latchingshutdownfunctionduringsuchacondition. Auto-Restart (UV resistor not present) In the event of a fault condition such as output overload, output short circuit or an open loop condition, PeakSwitch enters into auto-restart operation. An internal counter clockedbytheoscillatorisreseteverytimetheEN/UVpin is pulled low. When the EN/UV pin receives no feedback for 30 ms, the power MOSFET switching is disabled for 5 seconds (150 ms for the first auto-restart event). The auto-restart alternately enables and disables the switching ofthepowerMOSFETuntilthefaultconditionisremoved. Figure6illustratesauto-restartcircuitoperationinthepresence ofanoutputshortcircuit. Adaptive Switching Cycle On-time Extension Adaptiveswitchingcycleon-timeextensionkeepstheMOSFET onuntilcurrentlimitisreached,insteadofterminatingafter theDCMAXsignalgoeslow.Thison-timeextensionisadaptive becauseitonlyoccursaftertheENABLEpinhasbeenhigh forapproximately750s,aconditionthatwouldariseifthe MAX I DRAIN V DRAIN PI-2749-050301 Figure 7. PeakSwitch Operation at Near Maximum Loading. V EN CLOCK D MAX I DRAIN V DRAIN PI-2667-090700 Figure 8. PeakSwitch Operation at Moderately Heavy Loading. 5 Rev. I 10/06 PKS603-607 of a PeakSwitch design are constant, the power delivered to the load is proportional to the primary inductance of the transformerandpeakprimarycurrentsquared.Hence,designing thesupplyinvolvescalculatingtheprimaryinductanceofthe transformer for the maximum output power required. If the chosenPeakSwitchfamilymemberisappropriateforthepower level,thecurrentinthecalculatedinductancewillrampupto currentlimitbeforetheDCMAXlimitisreached. Enable Function PeakSwitchsensestheEN/UVpintodeterminewhetherornot toproceedwiththenextswitchingcycleasdescribedearlier. Thesequenceofcyclesisusedtodeterminethecurrentlimit. Onceacycleisstarted,italwayscompletesthecycle(evenwhen theEN/UVpinchangesstatehalfwaythroughthecycle).This operationresultsinapowersupplyinwhichtheoutputvoltage rippleisdeterminedbytheoutputcapacitor,amountofenergy perswitchcycleandthedelayofthefeedback. The EN/UV pin signal is produced on the secondary by comparingthepowersupplyoutputvoltagewithareference voltage.TheEN/UVpinsignalishighwhenthepowersupply outputvoltageislessthanthereferencevoltage. Inatypicalimplementation,theEN/UVpinisdrivenbyan optocoupler. The collector of the optocoupler transistor is connectedtotheEN/UVpinandtheemitterisconnectedto theSOURCEpin.TheoptocouplerLEDisconnectedinseries withaZenerdiodeacrosstheDCoutputvoltagetoberegulated. Whentheoutputvoltageexceedsthetargetregulationvoltage level(optocouplerLEDvoltagedropplusZenervoltage),the optocouplerLEDwillstarttoconduct,pullingtheEN/UVpin low.TheZenerdiodecanbereplacedbyaTL431reference circuitforimprovedaccuracy. ON/OFF Operation with Current-Limit State Machine TheinternalclockofthePeakSwitchrunsallthetime.Atthe beginningofeachclockcycle,itsamplestheEN/UVpinto decidewhetherornottoimplementaswitchcycle,andbased onthesequenceofsamplesovermultiplecycles,itdetermines theappropriatecurrentlimit.Athighloads,whentheEN/UV pinishigh(lessthan240Aoutofthepin),aswitchingcycle withthefullcurrentlimitoccurs.Atlighterloads,whenEN/UV ishigh,aswitchingcyclewithareducedcurrentlimitoccurs. V EN CLOCK D MAX I DRAIN V DRAIN PI-2661-072400 V EN CLOCK D Figure 10. PeakSwitch Operation at Very Light Loading. PI-4331-031506 200 100 0 5 I DRAIN V DC-INPUT MAX 0 300 200 100 V BYPASS V DRAIN V DRAIN 0 0 PI-2377-091100 5 10 Time (ms) Figure 9. PeakSwitch Operation at Medium Loading. Figure 11. PeakSwitch Power Up with Optional External UV Resistor (4 MW) Connected to EN/UV Pin. 6 Rev. I 10/06 PKS603-607 PI-4332-031506 PI-2395-030801 200 100 0 5 0 300 200 100 0 0 V DRAIN V BYPASS V DC-INPUT 200 100 0 400 300 200 100 0 V DRAIN V DC-INPUT Modifyingcurrentschematic 5 10 0 2.5 5 Time (ms) Figure 12. PeakSwitch Power Up Without Optional External UV Resistor Connected to EN/UV Pin. Time (s) Figure 14. Slow Power Down Timing With Optional External (4 MW) UV Resistor Connected to EN/UV Pin. 200 100 0 400 300 200 100 0 0 .5 V DRAIN V DC-INPUT Power Up/Down The PeakSwitch requires only a 0.33 F capacitor on the BYPASSpin.Becauseofitssmallsize,thetimetochargethis capacitoriskepttoanabsoluteminimum,typicallylessthan 1.5ms.DuetothefastnatureoftheON/OFFfeedback,there isnoovershootatthepowersupplyoutput.Whenanexternal resistorisconnectedfromthepositiveDCinputtotheEN/UV pin,thepowerMOSFETswitchingwillbedelayedduringpower upuntiltheDClinevoltageexceedsthethreshold(100V). Figures 11 and 12 show the power up timing waveform in applications with and without an external resistor (4 MW) connectedtotheEN/UVpin. During power down, when an external resistor is used, the powerMOSFETwillswitchfor30msaftertheoutputloses regulation.ThepowerMOSFETwillthenremainoffwithout anyglitchessincetheunder-voltagefunctionprohibitsrestart whenthelinevoltageislow. Figure13illustratesatypicalpower-downtimingwaveform. Figure14illustratesaveryslowpower-downtimingwaveform asinstandbyapplications.Anexternalresistorisconnectedto theEN/UVpininthiscasetopreventunwantedrestarts. Current Limit Operation EachswitchingcycleisterminatedwhentheDRAIN current reaches the current limit of the PeakSwitch. Current limit operationprovidesgoodlineripplerejection. BYPASS Pin Capacitor TheBYPASSpinusesasmall0.33uFceramiccapacitorfor decouplingtheinternalpowersupply. 1 Time (s) Figure 13. Normal Power Down Timing (Without UV). Atmaximumpeakload,PeakSwitchwillconductduringnearly allofitsclockcycles(Figure7).Attheratedcontinuousload, it will "skip" additional cycles in order to maintain voltage regulationatthepowersupplyoutput(Figure8).Atmedium loads, cycles will be skipped and the current limit will be reduced(Figure9).Atverylightloads,thecurrentlimitwill bereducedevenfurther(Figure10).Onlyasmallpercentage ofcycleswilloccurtosatisfytheinternalpowerconsumption ofthepowersupplyatno-load. The response time of the ON/OFF control scheme is very fast compared to normal PWM control. This provides tightregulationandexcellenttransientresponse. PI-2348-030801 7 Rev. I 10/06 PKS603-607 C10 1 nF 250 VAC R8 68 C11 1/2 W 330 pF D9 1N4148 C17 4.7 nF 1 kV D1-D4 1N4007 C4 150 F 400 V R15 2.2 R4 22 1/2 W D6 FR106 D5 1N4007 t RT1 10 O R9 C13 47 F 0.33 2W 16 V Q1 2N3906 30 V @ C14 L2 220 nF 1.07 A Cont. 2.7 A Peak 5.3 H 50 V C5 2.2 nF 1 kV VR1 1N4764A 100 V 1 9,10 D8 STPS3150 C12 330 F 50 V 7,8 R3 10 k 1/2 W 3 4 C6 47 F 35 V 5 T1 EE25 VR2 1N5255B 28 V R11 3 k R10 1.5 k RTN L1 5.3 mH R2 R1 1.3 M 1.3 M C3 680 nF X1 R5 2.2 M PeakSwitch D U1 PKS606Y C7 100 nF 400 V S 2 R12 1 k R7 4.7 k C15 100 nF 50 V D10 UF4003 VR3 1N5258B 36 V Q2 FS202DA R6 2.4 M D7 1N4148 C16 100 nF R14 100 R13 1 k R16 2.7 M EN/UV BP GND F1 3.15 A J1 L PE N C1-C2 100 pF 250 VAC C8 220 nF 50 V U2 PC817X4 RTN Connected to PE via Flying Lead C19 1 nF, 250 VAC J3 PCB Term 18 AWG PI-4170-060706 Figure 15. PeakSwitch PKS606Y, 32 W Continuous, 81 W Peak, Universal Input Power Supply. Application Example ThecircuitshowninFigure15isalowcost,highefficiency, flyback power supply designed to provide a 30 V, 1.06 A continuous,2.7Apeakoutputfromuniversalinputusingthe PKS606Y. Thesupplyfeaturesunder-voltagelockoutandsmart Csensewith A fastreset.Latchingoverload,openloop,andhystereticthermal shutdownprotectboththesupplyandloadunderfaultconditions whilehighefficiency(>80%)andverylowno-loadconsumption (<200mWat230VAC)meetsbothactiveandstandbyefficiency requirements.Outputregulationisaccomplishedusingasimple Zenerreferenceandoptocouplerfeedback. ComponentsC1,C2,C3,C10,C17,C19,R15,L1andL2provide commonmodeanddifferentialmodeEMIfiltering.Resistors R1andR2dischargeC3whenACpowerisremovedtoprevent electricshockfromtouchingtheACinput.ThermistorRT1 limitsthepeakinrushcurrentwhenACisfirstapplied. Therectifiedandfilteredinputvoltageisappliedtotheprimary windingofT1.Theothersideofthetransformerprimaryis drivenbytheintegratedMOSFETinU1.DiodeD6,C5,R3, R4,andVR1clamptheU1drainvoltagetosafelevels.Use of a fast diode (500 ns) vs ultrafast for D6 increases power supplyefficiencybyrecoveringsomeoftheclampenergy.A sloworstandardrecoverydiodemustnotbeusedduetothe highswitchingfrequency(aslowdiodewillnotrecoverfast enough under startup or output faults and therefore fail due toexcessdissipation).TheuseofaZenerinserieswithR3 comparedtoastandardRCDclampoptimizesbothEMIand energyefficiency. Components D5, C7, and R5-6 provideAC line and undervoltagesensingforPeakSwitchU1.Byprovidingaseparate rectifiedvoltageacrossC7whichisindependentfromtheload condition,ratherthanusingthemaininputcapacitor,allows PeakSwitch to distinguish the cause of loss of regulation. It alsoprovidesfastresetwhentheACinputisremoved,should latchingshutdownbetriggered.ConnectingR5andR6toC4 wouldstillprovideunder-voltagelockoutbutafterafaultthe userwouldhavetowaitforC4todischargebeforethesupply wouldreset.ResistorR16providesasmallamountofbiasto theU1ENABLE/UNDER-VOLTAGEpintoretaintheundervoltagelockoutfunctionduringbrown-outconditions. WithR5andR6present,switchingisinhibiteduntilthecurrent intotheEN/UVpinexceeds25A.Thisallowsthestartup voltagetobeprogrammedwithinthenormaloperatinginput voltagerange,preventingglitchingoftheoutputunderabnormal, lowvoltageconditionsandalsoonremovaloftheACinput. Underafaultcondition,forexampleanoutputshortcircuitor brokenfeedbackloop,ifthelinevoltageiswithinthenormal range(>25AintotheEN/UVpin)thePeakSwitchwilllatch 8 Rev. I 10/06 PKS603-607 offthepowersupply.Thisprotectstheloadandsupplyfrom acontinuousfaultcondition.RemovingtheACinputresets thiscondition. TheoutputvoltageisdeterminedbytheZenerdiodeVR2,the voltagedropacrossR12andtheforwarddropofD9andtheLED ofoptocouplerU2.ResistorR13providesbiascurrentthrough D9andVR2,toensurethatVR2isoperatingclosetoitsknee voltage,whileR12setstheoverallgainofthefeedbackloop. CapacitorC15boostshighfrequencyloopgaintohelpdistribute theenabledswitchingcyclesandreducepulsegrouping. Whentheoutputvoltageexceedsthefeedbackthresholdvoltage, currentwillflowintheoptocouplerLED,causingcurrentflowin thetransistoroftheoptocoupler.WhenthisexceedstheENABLE pinthresholdcurrentthenextswitchingcycleisinhibited,asthe outputvoltagefalls(belowthefeedbackthreshold)aconduction cycleisallowedtooccurandbyadjustingthenumberofenabled cyclesoutputregulationismaintained.Astheloadreduces thenumberofenabledcyclesdecreases,loweringtheeffective switchingfrequencyandscalingswitchinglosseswithload. This provides almost constant efficiency down to very light loads,idealformeetingenergyefficiencyrequirements. PeakSwitchdeviceU1issuppliedfromanauxillarywinding onthetransformerwhichisrectifiedandfilteredbyD7andC6. ResistorR7providesapproximately2mAofsupplycurrentinto theBYPASSpincapacitorC8.Duringstartuporfaultconditions whenthebiasvoltageislow,theBYPASSpinissuppliedfrom ahighvoltagecurrentsourcewithinU1,eliminatingtheneed forseparatestartupcomponents. Components Q1-2, R9-11, R14, C13, C16, and VR3 form anovervoltageandovercurrentprotectioncircuit.Anoutput overvoltageorovercurrentconditionfiresSCRQ2,clamping the output voltage and forcing PeakSwitch U1 into latching shutdownafter30ms.ThelowpassfilterformedbyR10and C13 adds a delay to the over-current sense. The shutdown conditioncanberesetbybrieflyremovingACpowerfor~3 seconds(maximum).ThelatchingfunctionwithinPeakSwitch significantlyreducesthesizeoftheSCRandoutputrectifier, D8,astheshortcircuitcurrentonlyflowsfor50msbeforethe supplylatchesoff. This design meets EN55022 Class B conducted EMI with >10dBmarginevenwiththeoutputRTNdirectlyconnected toearthground. themaximumpracticalcontinuousoutputpowerlevelthatcan beobtainedunderthefollowingassumedconditions: 1. The minimum DC input voltage is 100 V or higher for 85VACinput,or220Vorhigherfor230VACinputor single100/115VACwithavoltagedoubler. 2. Efficiency of 70% forY/F packaged devices, 75% for P packageddevicesat85-265VAC,75%for230VACinput allpackages 3. MinimumdatasheetvalueofI2f 4. Transformerprimaryinductancetoleranceof10% 5. Reflectedoutputvoltage(VOR)of135V 6. Voltageonlyoutputof15VwithanultrafastPNrectifier diode 7. ContinuousconductionmodeoperationwithtransientKP* valueof0.25 8. Sufficientheatsinkingisprovided,eitherexternally(Y/F packages)orthroughanareaofPCboardcopper(Ppackage) tokeeptheSOURCEpinortabtemperatureatorbelow 110C. 9. Deviceambienttemperatureof50Cforopenframedesigns and40Cforsealedadapters *Below a value of 1, KP is the ratio of ripple to peak primary current.Topreventreducedpowercapabilityduetopremature terminationofswitchingcycles,atransientKPlimitof0.25is recommended.Thisavoidstheinitialcurrentlimit(IINIT)being exceededatMOSFETturnon. Peak vs. Continuous Power PeakSwitch devices have current limit values that allow the specifiedpeakpowervaluesinthepowertable.Withsufficient heatsinking,thesepowerlevelscouldbeprovidedcontinuously, however this may not be practical in many applications. PeakSwitchisoptimizedforuseinapplicationsthathaveshort duration,highpeakpowerdemand,butasignificantlylower continuousoraveragepower.TypicalratioswouldbePPEAK 2xPAVE.ThehighswitchingfrequencyofPeakSwitchallows a small core size to be selected to deliver the peak power, buttheshortdurationpreventsthetransformerwindingfrom overheating.Asaveragepowerincreases,itmaybenecessaryto selectalargertransformertoallowincreasedcopperareaforthe windingsbasedonthemeasuredtransformertemperature. The power table provides some guidance between peak power and continuous power in sealed adapters, however specific applications may differ. For example, if the peak powerconditionisverylowdutycycle,saya2secondpeak occurring only at power up to accelerate a hard disk drive, then the transformer's thermal rise is only a function of the continuouspower.However,ifthepeakpoweroccursevery 200msfor50msthenitwouldneedtobeconsidered. Inallcases,theacceptabletemperatureriseofthePeakSwitch andtransformershouldbeverifiedunderworstcaseambient andloadconditions. Key Application Considerations PeakSwitch Design Considerations Output Power Table Thedatasheetmaximumoutputpowertable(Table1)represents Rev. I 10/06 PKS603-607 Power (W) P3 provides sufficient margin to prevent core saturation under startuporoutputshortcircuitconditions. Optocoupler CTR To minimize the delay introduced by the optocoupler, it is recommendedthatahigh(300-600%)CTRoptocouplerisused inPeakSwitchdesigns. PI-4329-030906 P2 P1 t1 T t2 Time (t) Bias Winding AllPeakSwitchdesignsmustuseabiaswindingtofeedoperating currentintotheBYPASSpinoncethesupplyisoperational. Itisrecommendedthatthevalueoftheresistorfromthebias windingtotheBYPASSpinbeselectedsuchthatitsuppliesthe samecurrentasthemaximumdatasheetdrainsupplycurrent (IS2)forthespecificdevicebeingused. PeakSwitch Layout Considerations See Figure 17 for a recommended circuit board layout for PeakSwitch. Single Point Grounding DevicesinYandFpackageshaveseparatereturnpinsforthe MOSFET source (S) and the controller (GND) connections which are internally connected. Therefore connecting these pinsonthePCboardisnotrecommended. Devices in the P package do not have separate return pins, but in both cases the low current feedback signals and IC decoupling,highMOSFETcurrentandbiaswindingprimary returnconnectionshouldroutethroughseparatetracestothe Kelvinconnection. Thebiaswindingreturnconnectionistreatedseparately,even thoughitcarrieslowcurrent.Toroutehighcurrentsawayfrom thedevicewhenthesupplyissubjectedtolinesurgetransients, thebiaswindingshouldbereturneddirectlytotheinputbulk capacitor. Bypass Capacitor (CBP) TheBYPASSpincapacitorshouldbelocatedascloseaspossible totheBYPASSandSOURCEpins. Primary Loop Area The area of the primary loop that connects the input filter capacitor,transformerprimaryandPeakSwitchtogethershould bekeptassmallaspossible. Primary Clamp Circuit AclampisusedtolimitthepeakvoltageontheDRAINpin atturnoff.ThiscanbeachievedbyusinganRCDclampora Zener(~200V)anddiodeclampacrosstheprimarywinding. InallcasestominimizeEMIcareshouldbetakentominimize thecircuitpathfromtheclampcomponentstothetransformer andPeakSwitch. Figure 16. Continuous (Average) Output Power Calculation Example. Figure 16 shows how to calculate the average power requirementsforadesignwithtwodifferentpeakloadconditions. WherePXarethedifferentoutputpowerconditions,tXarethe durationsofeachpeakpowercondition,andTistheperiodof onecycleofthepulseloadcondtion. Audible Noise The cycle skipping mode of operation used in PeakSwitch cangenerateaudiofrequencycomponentsinthetransformer. Tolimitthisaudiblenoisegeneration,thetransformershould be designed such that the peak core flux density is below 3000Gauss(300mT).Followingthisguidelineandusingthe standardtransformerproductiontechniqueofdipvarnishing practically eliminates audible noise. Vacuum impregnation ofthetransformershouldnotbeusedduetothehighprimary capacitanceandincreasedlossesthatresult. CeramiccapacitorsthatusedielectricssuchasZ5U,whenused inclampcircuits,mayalsogenerateaudionoise.Ifthisisthe casetryreplacingthemwithacapacitorhavingadifferenttypeof dielectricorconstruction,forexampleafilmtypecapacitor. Maximum Flux Density Amaximumvalueof3000Gaussduringnormaloperationis recommendedtolimitthemaximumfluxdensityunderstart upandoutputshortcircuit.Undertheseconditionstheoutput voltageislowandlittleresetofthetransformeroccursduring theMOSFETofftime.Thisallowsthetransformerfluxdensity to staircase above the normal operating level. A value of 3000Gaussatthepeakcurrentlimitoftheselecteddevice, together with the built in protection features of PeakSwitch 10 Rev. I 10/06 PKS603-607 Safety Spacing Y1Capacitor Maximize hatched copper areas ( ) for optimum heatsinking Output Rectifier Output Filter Capacitor + HV Input Filter Capacitor PRI BIAS D PRI T r a n s f o r m e r SEC - S S PeakSwitch EN/UV BP S BIAS TOP VIEW S CBP Optocoupler - (a) Safety Spacing + Input Filter Capacitor Y1Capacitor DC + OUT PI-4326-060706 Maximize hatched copper areas ( ) for optimum heatsinking HV Output Rectifier PRI T r a n s f o r m e r Output Filter Capacitor - SEC NC EN/UV GND D PRI BIAS BIAS BP TOP VIEW CBP Heat Sink Optocoupler (b) Figure 17. Recommended Layout for PeakSwitch in (a) P and (b) Y/F Packages. - DC + OUT PI-4327-031706 11 Rev. I 10/06 PKS603-607 Thermal Considerations For the P package, the four SOURCE pins are internally connectedtotheICleadframeandprovidethemainpathto removeheatfromthedevice.Therefore,alltheSOURCEpins shouldbeconnectedtoacopperareaunderneaththePeakSwitch toactnotonlyasasinglepointground,butalsoasaheatsink. Asthisareaisconnectedtothequietsourcenode,itshouldbe maximizedforgoodheatsinking.Similarly,foraxialoutput diodes,maximizethePCBareaconnectedtothecathode. Y-Capacitor TheplacementoftheY-typecapshouldbedirectlyfromthe primaryinputfiltercapacitorpositiveterminaltothecommon/ return terminal of the transformer secondary. If a second Y-typecapisrequiredfromprimarytosecondaryreturn,connect theprimarysidedirectlytothenegativeterminaloftheinput capacitor.Suchaplacementwillroutehighmagnitudecommon modesurgecurrentsawayfromthePeakSwitchdevice.Note -ifaninput(C,L,C)EMIfilterisused,thentheinductorin thefiltershouldbeplacedbetweenthenegativeterminalson theinputfiltercapacitors. Optocoupler Place the optocoupler physically close to the PeakSwitch to minimizetheprimarysidetracelengths.Keepthehighcurrent highvoltagedrainandclamptracesawayfromtheoptocoupler topreventnoisepickup. Output Diode For best performance, the area of the loop connecting the secondary winding, the output diode and the output filter capacitorshouldbeminimized.Inaddition,sufficientcopper area should be provided at the anode and cathode terminal ofthediodeforheatsinking.Alargerareaispreferredatthe quitecathodeterminal.Alargeanodeareacanincreasehigh frequencyradiatedEMI. Quick Design Checklist As with any power supply design, all PeakSwitch designs shouldbeverifiedonthebenchtomakesurethatcomponent specificationsarenotexceededunderworstcaseconditions.The followingminimumsetoftestsisstronglyrecommended: 1. Maximumdrainvoltage-VerifythattheVDSdoesnotexceed 650Vathighestinputvoltageandpeak(overload)output power.The50Vmargintothe700VBVDSSspecification allowsmarginfordesignvariation. 2. Maximumdraincurrents-Verifythesimultaneousdrain voltageandcurrentlevelsarewithinthecurveprovidedin Figure29underworstcaseconditions.Typicallythisoccurs atstartup(andduringanoutputshortcircuit),highestinput line voltage and maximum ambient temperature. When makingthismeasurementusingacurrentprobe,tomonitor thedraincurrent,ensuretheresultsarecorrectedforthe 10-20nscurrentprobedelay. 3. Maximumdraincurrent-Atmaximumambienttemperature, maximuminputvoltageandpeakoutput(overload)power, verifydraincurrentwaveformsshownosignsoftransformer saturation. If the transformer shows signs of saturation, it should be redesigned with a lower flux density, or a higher quality corematerial should beused. To prevent false triggering of the current limit, verify the leading edgecurrentspikeeventisbelowIINIT(MIN)attheendofthe tLEB(MIN).Underallconditions,themaximumdraincurrent shouldbebelowtheabsolutemaximumlimitspecifiedin theAbsoluteMaximumRatingssection. 4. Thermal Check - At specified maximum output power, minimuminputvoltageandmaximumambienttemperature, verifythatthetemperaturespecificationsarenotexceededfor PeakSwitch,transformer,outputdiodeandoutputcapacitors. Enoughthermalmarginshouldbeallowedforpart-to-part variationoftheRDS(ON)ofPeakSwitchasspecifiedinthe datasheet.Underlowline,maximumpower,amaximum PeakSwitchSOURCEpinortabtemperatureof110Cis recommendedtoallowforthesevariations. Design Tools Up-to-date information on design tools can be found at the PowerIntegrationswebsite:www.powerint.com. 12 Rev. I 10/06 PKS603-607 ABSOLUTE MAXIMUM RATINGS(1,) DRAINVoltage...............................................-0.3Vto700V . DRAINPeakCurrent:............................. 2xILIMIT(Typical)(5) EN/UVVoltage....................................................-0.3Vto9V EN/UVCurrent........................................................... 100mA BYPASSVoltage.................................................. 0.3Vto9V StorageTemperature......................................-65Cto150C OperatingJunctionTemperature(2).................-40Cto150C LeadTemperature(3)....................................................... 260C Notes: 1. AllvoltagesreferencedtoSOURCE,TA=25C. 2. Normallylimitedbyinternalcircuitry. 3. 1/16in.fromcasefor5seconds. 4.Maximumratingsspecifiedmaybeappliedoneatatime, withoutcausingpermanentdamagetotheproduct. ExposuretoAbsoluteMaximumRatingconditionsfor extendedperiodsoftimemayaffectproductreliability. 5. PeakDRAINcurrentisallowedwhiletheDRAINvoltage issimultaneouslylessthan400V.SeealsoFigure29. ThermalImpedance:Y/FPackage: (qJA)(1)........................................80C/W (qJC)(2)..........................................2C/W PPackage: (qJA).....................70C/W(3);60C/W(4) (qJC)(5).....................................10C/W(5) THERMAL IMPEDANCE Notes: 1. Freestandingwithnoheatsink. 2. Measuredatthebacksurfaceoftab. 3. Solderedto0.36sq.in.(232mm2),2oz.(610g/m2)copperclad. 4. Solderedto1sq.in.(645mm2),2oz.(610g/m2)copperclad. 5. MeasuredontheSOURCEpinclosetoplasticinterface. Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C See Figure 18 (Unless Otherwise Specified) TJ = 25 C See Figure 4 Average Peak-Peak Jitter S1 Open Conditions Min Typ Max Units CONTROL FUNCTIONS Output Frequency Maximum Duty Cycle EN/UV Pin Turn Off Threshold Current EN/UV Pin Voltage fOSC DCMAX IDIS IEN/UV = -125 A IEN/UV = 25 A VEN/UV = 0 V EN/UV Open (MOSFET Switching) See Note A, B VBP = 0 V, TJ = 25 C See Note C VBP = 4 V, TJ = 25 C See Note C PKS603 PKS604 PKS605 PKS606 PKS607 PKS603-604 PKS605-607 PKS603-604 PKS605-607 250 62 277 16 65 68 304 kHz % -350 0.4 1.3 350 460 600 700 950 1160 -7.5 -10.0 -4.5 -6.5 -240 1.0 2.0 475 570 725 875 1175 1430 -5.0 -6.6 -3.0 -4.5 -200 1.5 2.7 600 690 870 1050 1400 1700 -2.5 -3.2 -1.5 -2.5 A VEN IS1 V DRAIN Supply Current IS2 A BYPASS Pin Charge Current ICH1 ICH2 mA 13 Rev. I 10/06 PKS603-607 Conditions Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C See Figure 18 (Unless Otherwise Specified) Min Typ Max Units CONTROL FUNCTIONS (cont.) BYPASS Pin Shunt V BP(SH) Regulator Voltage BYPASS Pin VBP Voltage BYPASS Pin VBPH Voltage Hysteresis EN/UV Pin Line ILUV Under-Voltage Threshold CIRCUIT PROTECTION See Note D 6.0 5.5 0.8 6.3 5.8 1.0 25 6.7 6.15 1.3 27.5 V V V A TJ = 25 C 22.5 PKS603 P TJ = 25 C PKS604 P/Y/F TJ = 25 C PKS605 P TJ = 25 C di/dt = 200 mA/s See Note E di/dt = 290 mA/s See Note E di/dt = 290 mA/s See Note E di/dt = 325 mA/s See Note E di/dt = 255 mA/s See Note E di/dt = 660 mA/s See Note E di/dt = 800 mA/s di/dt = 200 mA/s di/dt = 290 mA/s di/dt = 290 mA/s di/dt = 325 mA/s di/dt = 255 mA/s di/dt = 660 mA/s di/dt = 800 mA/s 0.75 1.35 1.35 1.76 1.40 2.60 2.79 164 524 524 890 569 1955 2242 0.81 1.45 1.45 1.89 1.51 2.80 3.00 182 582 582 989 632 2172 2493 0.87 1.55 1.55 2.02 1.62 3.00 3.21 204 652 652 1108 708 2433 2793 A2kHz A Current Limit ILIMIT PKS605 Y/F TJ = 25 C PKS606 P TJ = 25 C PKS606 Y/F TJ = 25 C PKS607 Y/F TJ = 25 C PKS603 P TJ = 25 C PKS604 P/Y/F TJ = 25 C PKS605 P TJ = 25 C Power Coefficient I2f PKS605 Y/F TJ = 25 C PKS606 P TJ = 25 C PKS606 Y/F TJ = 25 C PKS607 Y/F TJ = 25 C 1 Rev. I 10/06 PKS603-607 Conditions Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 C See Figure 18 (Unless Otherwise Specified) See Figure 21 See Note F TJ = 25 C See Note F TJ = 25 C See Notes F, G Min Typ Max Units CIRCUIT PROTECTION (cont.) Initial Current Limit Leading Edge Blanking Time Current Limit Delay Thermal Shutdown Temperature Thermal Shutdown Hysteresis OUTPUT PKS603 ID = 81 mA PKS604 ID = 150 mA TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C 7.8 11.7 5.2 7.8 3.9 5.8 2.6 3.9 2.0 3.0 9.0 13.5 6.0 9.0 4.5 6.7 3.0 4.5 2.3 3.5 W IINIT tLEB tILD 0.75 x ILIMIT(Min) 170 215 150 135 142 75 150 mA ns ns C C ON-State Resistance RDS(ON) PKS605 ID = 200 mA PKS606 ID = 300 mA PKS607 ID = 300 mA OFF-State Drain Leakage Current IDSS1 VBP = 6.2 V VEN/UV = 0 V VDS = 560 V TJ = 125 C See Note H VBP = 6.2 V VEN/UV = 0 V VDS = 375 V TJ = 50 C See Note H 700 50 15 200 A IDSS2 Breakdown Voltage Drain Supply Voltage Output EN/UV Delay Output Disable Setup Time BVDSS VBP = 6.2 V, VEN/UV = 0 V, See Note I, TJ = 25 C V V 5 0.5 s s tEN/UV tDST See Figure 20 15 Rev. I 10/06 PKS603-607 Conditions Parameter OUTPUT (cont.) Auto-Restart ON Time Auto-Restart OFF Time Symbol SOURCE = 0 V; TJ = -40 to 125 C See Figure 18 (Unless Otherwise Specified) TJ = 25 C See Note J See Note K Min Typ Max Units tAR tAROFF 30 5 ms s NOTES: A. Total current consumption is the sum of IS1 and IDSS when EN/UV pin is shorted to ground (MOSFET not switching) and the sum of IS2 and IDSS when EN/UV pin is open (MOSFET switching). B. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BYPASS pin current at 6.1 V. C. See Typical Performance Characteristics section for BYPASS pin startup charging waveform. D. BYPASS pin is externally supplied (bias winding). E. For current limit at other di/dt values, refer to Figure 25. F. This parameter is derived from characterization. G. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT specification. H. IDSS1 is the worst case OFF state leakage specification at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical specification under worst case application conditions (rectified 265 VAC) for no-load consumption calculations. I. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not exceeding minimum BVDSS. J. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). Auto-restart on time is extended during startup and certain fault conditions because the controller reduces its oscillator clock frequency to prevent excessive drain currents. If excessive drain currents are still occuring half way through the auto-restart on time, output MOSFET switching is disabled for the remainder of that auto-restart on time episode (if the line is not sensed) or the supply latches off (if the line is sensed and adequate line voltage is present). K. Only applicable if no UV resistor is present at the EN/UV pin. 5 s applies only if the preceding switching autorestart event did not result in EN/UV pin going low. In that event, the first auto-restart off-time is 150 ms. 16 Rev. I 10/06 PKS603-607 470 W 5W 470 W S S S EN/UV BP D S2 S1 4 MW 10 V 0.33 F 150 V 50 V S NOTE: This test circuit is not applicable for current limit or output characteristic measurements. PI-4317-030606 Figure 18. PeakSwitch General Test Circuit. (internal signal) tP DCMAX EN/UV VDRAIN tP = 1 fOSC PI-2364-012699 tEN/UV Figure 19. Duty Cycle Measurement. Figure 20. Output Enable Timing. tLEB (Blanking Time) 0.8 IINIT(MIN) ILIMIT(MIN) @ 100 C Figure 21. Current Limit Envelope. PI-4328-030806 17 Rev. I 10/06 PKS603-607 Typical Performance Characteristics PI-2213-012301 PI-4294-022806 1.1 1.2 1.0 0.8 0.6 0.4 0.2 0 Breakdown Voltage (Normalized to 25 C) 1.0 0.9 -50 -25 0 25 50 75 100 125 150 Output Frequency (Normalized to 25 C) -50 -25 0 25 50 75 100 125 Junction Temperature (C) Figure 22. Breakdown vs. Temperature. PI-4295-020806 Junction Temperature (C) Figure 23. Frequency vs. Temperature. PI-4297-020806 1.2 1.4 Standard Current Limit (Normalized to 25 C) 1 0.8 0.6 0.4 0.2 0 -50 Normalized Current Limit 1.2 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 1 2 3 4 Junction Temperature (C) Figure 24. Standard Current Limit vs. Temperature. PI-4307-091206 Normalized di/dt Figure 25. Current Limit vs. di/dt. PI-4308-091206 1.2 1.0 1000 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 Scaling Factors: PKS603 1.0 PKS604 1.5 PKS605 2.0 PKS606 3.0 PKS607 4.0 TJ = 25 C TJ = 100 C Drain Capacitance (pF) Drain Current (A) 100 Scaling Factors: PKS603 1.0 PKS604 1.5 PKS605 2.0 PKS606 3.0 PKS607 4.0 10 1 0 100 200 300 400 500 600 Drain Voltage (V) Figure 26. Output Characteristic. Drain Voltage (V) Figure 27. COSS vs. Drain Voltage. 18 Rev. I 10/06 PKS603-607 Typical Performance Characteristics (cont.) PI-4296-020806 PI-4330-031606 1.2 2.5 Under-Voltage Theshold (Normalized to 25 C) 1 0.8 0.6 0.4 0.2 0 -50 Drain Current (Normalized to Typical ILIMIT) 2 1.5 1 0.5 0 50 100 150 0 0 100 200 300 400 500 600 700 800 Junction Temperature (C) Figure 28. Under-Voltage Threshold vs. Temperature. Drain Voltage (V) Figure 29. Maximum Allowable Drain Current vs. Drain Voltage. 1 Rev. I 10/06 PKS603-607 PART ORDERING INFORMATION PeakSwitch Product Family Series Number Package Identifier P Y F Plastic DIP-8C Plastic TO-220-7C Plastic TO-262-7C Pure Matte Tin (Pb-Free) Lead Finish PKS 60 P N N TO-220-7C .390 (9.91) .420 (10.67) + .165 (4.19) .185 (4.70) .146 (3.71) .156 (3.96) .045 (1.14) .055 (1.40) .108 (2.74) REF .234 (5.94) .261 (6.63) .570 (14.48) REF. 7 TYP. .080 (2.03) .120 (3.05) .670 (17.02) REF. .461 (11.71) .495 (12.57) .860 (21.84) .880 (22.35) .068 (1.73) MIN PIN 1 PIN 1 & 7 PIN 2 & 4 .024 (.61) .010 (.25) M .034 (.86) .050 (1.27) BSC .150 (3.81) BSC .012 (.30) .024 (.61) .190 (4.83) .210 (5.33) .040 (1.02) .060 (1.52) .040 (1.02) .060 (1.52) .050 (1.27) .050 (1.27) .050 (1.27) .050 (1.27) .200 (5.08) .100 (2.54) PIN 1 PIN 7 Notes: 1. Controlling dimensions are inches. Millimeter dimensions are shown in parentheses. 2. Pin numbers start with Pin 1, and continue from left to right when viewed from the front. 3. Dimensions do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15mm) on any side. 4. Minimum metal to metal spacing at the package body for omitted pin locations is .068 in. (1.73 mm). 5. Position of terminals to be measured at a location .25 (6.35) below the package body. 6. All terminals are solder plated. .180 (4.58) .150 (3.81) .150 (3.81) Y07C MOUNTING HOLE PATTERN PI-2644-122004 20 Rev. I 10/06 PKS603-607 DIP-8C -E- D S .004 (.10) .240 (6.10) .260 (6.60) Pin 1 -D.367 (9.32) .387 (9.83) .057 (1.45) .068 (1.73) (NOTE 6) .125 (3.18) .145 (3.68) .015 (.38) MINIMUM Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 4. Pin locations start with Pin 1, and continue counter-clockwise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T. -T- SEATING PLANE .120 (3.05) .140 (3.56) .048 (1.22) .053 (1.35) .137 (3.48) MINIMUM .008 (.20) .015 (.38) .300 (7.62) BSC (NOTE 7) .300 (7.62) .390 (9.91) .100 (2.54) BSC .014 (.36) .022 (.56) T E D P08C PI-3933-100504 S .010 (.25) M 21 Rev. I 10/06 PKS603-607 TO-262-7C .390 (9.91) .420 (10.67) .055 (1.40) .066 (1.68) .326 (8.28) .336 (8.53) .795 (20.18) REF. .165 (4.17) .185 (4.70) .045 (1.14) .055 (1.40) 7 TYP. .080 (2.03) .120 (3.05) .495 (12.56) REF. .595 (15.10) REF. PIN 1 .068 (1.73) MIN .024 (.61) .010 (.25) M .034 (.86) .050 (1.27) BSC .150 (3.81) BSC PIN 1 & 7 PIN 2 & 4 .012 (.30) .024 (.61) .190 (4.83) .210 (5.33) .040 (1.02) .060 (1.52) .040 (1.06) .060 (1.52) .050 (1.27) .050 (1.27) .050 (1.27) .050 (1.27) .200 (5.08) .100 (2.54) PIN 1 PIN 7 .180 (4.58) .150 (3.81) .150 (3.81) F07C MOUNTING HOLE PATTERN Notes: 1. Controlling dimensions are inches. Millimeter dimensions are shown in parentheses. 2. Pin numbers start with Pin 1, and continue from left to right when viewed from the front. 3. Dimensions do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15mm) on any side. 4. Minimum metal to metal spacing at the package body for omitted pin locations is .068 inch (1.73 mm). 5. Position of terminals to be measured at a location .25 (6.35) below the package body. 6. All terminals are solder plated. PI-2757-122004 22 Rev. I 10/06 PKS603-607 23 Rev. I 10/06 PKS603-607 Revision Notes G H I F Date 3/06 4/06 6/06 8/06 1)FinalReleaseDataSheet. ReviseddevicesymbolinFigures1and15tobeconsistentwithotherPIdocumentation(addedsecond groundconnection).RevisedlayoutofFigure17(PI-4326). RevisedgroundinginFigure1tomatchactualimplementation. AddedPKS607. For the latest updates, visit our website:www.powerint.com PowerIntegrationsreservestherighttomakechangestoitsproductsatanytimetoimprovereliabilityormanufacturability.PowerIntegrationsdoesnotassume anyliabilityarisingfromtheuseofanydeviceorcircuitdescribedherein.POWERINTEGRATIONSMAKESNOWARRANTYHEREINANDSPECIFICALLY DISCLAIMSALLWARRANTIESINCLUDING,WITHOUTLIMITATION,THEIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORA PARTICULARPURPOSE,ANDNON-INFRINGEMENTOFTHIRDPARTYRIGHTS. PATENT INFORMATION Theproductsandapplicationsillustratedherein(includingtransformerconstructionandcircuitsexternaltotheproducts)maybecoveredbyoneormoreU.S. andforeignpatents,orpotentiallybypendingU.S.andforeignpatentapplicationsassignedtoPowerIntegrations.AcompletelistofPowerIntegrations'patents maybefoundatwww.powerint.com.PowerIntegrationsgrantsitscustomersalicenseundercertainpatentrightsassetforthathttp://www.powerint.com/ip.htm. LIFE SUPPORT POLICY POWERINTEGRATIONS'PRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESORSYSTEMS WITHOUTTHEEXPRESSWRITTENAPPROVALOFTHEPRESIDENTOFPOWERINTEGRATIONS.Asusedherein: 1.ALifesupportdeviceorsystemisonewhich,(i)isintendedforsurgicalimplantintothebody,or(ii)supportsorsustainslife,and(iii)whosefailuretoperform, whenproperlyusedinaccordancewithinstructionsforuse,canbereasonablyexpectedtoresultinsignificantinjuryordeathtotheuser. 2.Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocausethefailureofthelife supportdeviceorsystem,ortoaffectitssafetyoreffectiveness. ThePIlogo,TOPSwitch, TinySwitch,LinkSwitch, DPA-Switch,PeakSwitch,Clampless,EcoSmart,E-Shield, Filterfuse,StackFET,PI ExpertandPI FACTS aretrademarksofPowerIntegrations,Inc.Othertrademarksarepropertyoftheir respectivecompanies.(c)Copyright2006,PowerIntegrations,Inc. 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